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Short description
The modul VVL (vehicle velocity limitation) sets actual velocity limit, considered limits are:

- general velocity limit (through adjustment channel)

- velocity limit for transport mode
Interface description
The signals and parameter files for the relevante SWRS are:


The valid versions of the signals and parameter files to be find in SWRS SWC_VMMP (SWRS_Id 1078981): Chapter 2 "Interface description".
The valid version of the signal and parameter files for test basis to be find in CG, which to be tested.
Presetting/Framework/Definitions
Toolchain
The Matlab/Simulink/TargetLink versions have to be used according to the HCP1-Toolchain.
For modeling in Simulink the valid EnProVe catalogue of guidelines has to be used.
Tolerances
The allowed B2B deviation for all output-signals to the expected reactions is defined by the following tolerances:
Bool: No deviation allowed
UInt, Int: No deviation allowed
Float: 0.1% related to the permissible value range of the signal
It must be ensured that an output reaction occurs due to an event at the input within the same calculation step.
Conditions
NVM simulation
NVM signals

NVM (non-volatile memory) output signals are used to store information being calculated in the last time sample before ECU shutdown during ECU sleep. By reading the corresponding NVM input signals, the stored values are available in the first time sample after ECU startup again. While the ECU is awake, the value of an NVM input signal is equal to the value of the corresponding NVM output signal of the previous time sample.

To simulate this signal behavior NVM input signals have to be stimulated as described below:

In the first time step the value of each NVM input signal has to be stimulated with the default value defined below. Once the value of the corresponding NVM output signal is available (starting from second time step), each NVM input signal has to be stimulated with the corresponding NVM output signal (feedback loop with a delay of one time step).

NVM_Input[t] = NVM_Output[t-1]

Input Conditions
If not requested differently, the following default signal values must be applied during each test case.
Signal and parameters state are added since they are not visible in SPE. As soon as the state will be added in SPE, they will not be valid anymore in this SWRS (SPE = master).
VMM1

VMMP_s_DWDRead_VVehLimBwd
VMM2

VMMP_s_DWDRead_VVehLimFwd
VMM3

VMMP_s_DWDRead_VVehLimReq

0 = Init

1 = No Request

2 = Write Request
VMM4

VMMP_s_DWDRead_NumVehLimChk
VMM6

VMMP_s_DWDRead_VVehLimProd
VMM7

VMMP_s_DWDRead_VVehLimProdReq

0 = Init

1 = No Request

2 = Write Request
VMM8

VMMP_s_NVMBlck03_IniErrSt

0 = OK

1 = NOK
VMM9

VMMP_s_NVMBlck04_IniErrSt

0 = OK

1 = NOK
SRV1 

VSOEM_s_VLgtStdDev
SRV2

VSOEM_s_VLgtVehNrm
SRV3

VSOVD_s_StDrvDir

DrvDirBwd = 2
SRV4

VSOVD_s_StTrptProt
SRV9

VSOVD_s_StCrExchProt
SRV10

VSOVD_s_StProdMd
SRV12

VSOVD_s_VehPwrLvl
SRV13

VSOVD_s_StPwrMd
NVM1

VMMP_s_NVM08Read_VVehLimFwd
NVM2

VMMP_s_NVM09Read_VVehLimBwd
NVM3

VMMP_s_NVM10Read_NumVehLimChk
NVM5

VMMP_s_NVM11Read_FlgVehLimVld
NVM6

VMMP_s_NVM12Read_VVehLimProd
Parameters
P1

VMMP_VVL_p_VVehLimWithStdDev

0 = correction with standard deviation NOT active 

1 = correction with standard deviation active 

2 = correction with 3sigma active
P2

VMMP_VVL_p_VVehLimTrptProtFwd
P3

VMMP_VVL_p_VVehLimTrptProtBwd
P4

VMMP_VVL_p_VVehLimTrptProtAcv
P5

VMMP_VVL_p_VVehLimAdjChnAcv
P6

VMMP_VVL_p_VVehLimFwdDft
P7

VMMP_VVL_p_VVehLimBwdDft
P9

VMMP_VVL_p_VVehLimStAcvFwd
P10

VMMP_VVL_p_SimVVehLimFwd
P11

VMMP_VVL_p_SimVVehLimBwd
P12

VMMP_VVL_p_SimSwt
P13

VMMP_VVL_p_SimSwtVVehLim
P14

VMMP_VVL_p_SimVVehLimSt
P15

VMMP_VVL_p_SimSwtVVehLimSt
P16

VMMP_VVL_p_SimNumVehLimChk
P20

VMMP_VVL_p_SwtUseStDrvDir
P22 

VMMP_VVL_p_DTCAdjChnVVehLimProdAcv
P23

VMMP_VVL_p_DTCAdjChnVVehLimQTSAcvAcv
P24 

VMMP_VVL_p_DTCAdjChnVVehLimCRCNotVldAcv
P25

VMMP_VVL_p_SwtVVehLimCl15Avl
P26

VMMP_VVL_p_VVehLimVThAvl
P27

VMMP_VVL_p_SwtVVehLimVThAvl
P28

VMMP_VVL_p_VVehLimBwdMaxVal
P29

VMMP_VVL_p_VVehLimProdVThAvl
P30

VMMP_VVL_p_AdjChnErrCodNoErr
P31

VMMP_VVL_p_AdjChnErrCodOutOfRng
P32

VMMP_VVL_p_AdjChnErrCodCl15Off
P33

VMMP_VVL_p_AdjChnErrCodVToHi
P34

VMMP_VVL_p_AdjChnErrCodProdMdNotAcv
P35

VMMP_VVL_p_AdjChnErrCodDrvReqAcv
P36

VMMP_VVL_p_AdjChnErrCodPTPwrNotOff
P37

VMMP_VVL_p_VVehLimProdVNotVldValMin
P38

VMMP_VVL_p_VVehLimProdVNotVldValMax
P39

VMMP_VVL_p_SimVVehLimProdFwd
P40

VMMP_VVL_p_SimSwtVVehLimProd
P41

VMMP_VVL_p_SimSwtVVehLimProdSt
P42

VMMP_VVL_p_SimVVehLimProdSt
P43

VMMP_VVL_p_VVehLimProdNotAcvRst
P44

VMMP_VVL_p_VVehBwdTh
P45

VMMP_VVL_p_VVehLimFwdMaxVal
P46

VMMP_VVL_p_AdjChnProdPreCndAcv
P47

VMMP_VVL_p_VVehLimAdjChnProdAcv
P48

VMMP_VVL_p_SetDftGetErrStAcv
P49

VMMP_VSOVD_c_StPwrMdPwrOffMd
P50

VMMP_VVL_p_WLVMaxAcv
P51

VMMP_VVL_p_VVehLimSigStdDev
P52

VMMP_VVL_p_DTCAdjChnVVehLimNotAcvAcv
Predefinitions
VVLPC1 

Driving direction backward

IF OR(1,2)

1) the driving direction  is backwards

2) the driving direction  is smaller zero

THEN

the driving direction is backwards VVLPC1
VVLPC2 

CANCRC check is successful

To verify the value of adjustment channel VVehLimFwd  and VVehLimBwd  with CRC checksum  a CANCRC check is implemented.

IF

value fwd  and value bwd  are leading to a checksum 

THEN

the CANCRC check is successful VVLPC2
CANCRC check:

- the CRC uses the start value 65535

- the CRC uses the polynom 50585 (=CANCRC)

- the CRC starts with the value for fwd und continues with the value for bwd

algorithm:

1) extract byte3 and shift it 16 positions to the right

2) XOR-connect the result with the start value

3) repeat this step for (in total) 8 times:

bitshift 1 position to the left and extract bit 16.

if bit 16 is

 - 0, then AND-connet the result with 0xFFFF (clear the upper 16 bits)

 - 1, then XOR-connect the result with the polynom and AND-connect it with 0xFFFF (clear the uper 16 bits)

4) continue with byte2, repeat step 1-3 for byte 2 and use the result of byte 3 as start value

5) continue with byte1, repeat step 1-3 for byte 2 and use the result of byte 2 as start value

6) continue with byte0, repeat step 1-3 for byte 2 and use the result of byte 1 as start value

7) continue with byte3 of value for bwd, use the result of byte0 of fwd as start value.

...

at the end, convert the result to a uint16.
Reactions
VVL1

VVL_s_LgtLimV_StAcvFwd

0 = Passive 

1 = Active 

3 = Failure 

6 = Init

Record #	Row	ID	Role	Normalized source text
25850	2	16648279	context	Short description Short description
25851	3	16648280	context	The modul VVL (vehicle velocity limitation) sets actual velocity limit, considered limits are: - general velocity limit (through adjustment channel) The modul VVL (vehicle velocity limitation) sets actual velocity limit, considered limits are: - general velocity limit (through adjustment channel) - velocity limit for transport mode
25852	4	16648281	context	Interface description Interface description
25853	5	16648282	context	The signals and parameter files for the relevante SWRS are: The signals and parameter files for the relevante SWRS are:
25854	6	16648283	context
25855	7	16648284	context
25856	8	16648285	context	The valid versions of the signals and parameter files to be find in SWRS SWC_VMMP (SWRS_Id 1078981): Chapter 2 "Interface description". The valid versions of the signals and parameter files to be find in SWRS SWC_VMMP (SWRS_Id 1078981): Chapter 2 "Interface description".
25857	9	16648286	context	The valid version of the signal and parameter files for test basis to be find in CG, which to be tested. The valid version of the signal and parameter files for test basis to be find in CG, which to be tested.
25858	10	16648287	context	Presetting/Framework/Definitions Presetting/Framework/Definitions
25859	11	16648288	context	Toolchain Toolchain
25860	12	16648289	context	The Matlab/Simulink/TargetLink versions have to be used according to the HCP1-Toolchain. The Matlab/Simulink/TargetLink versions have to be used according to the HCP1-Toolchain.
25861	13	16648290	context	For modeling in Simulink the valid EnProVe catalogue of guidelines has to be used. For modeling in Simulink the valid EnProVe catalogue of guidelines has to be used.
25862	14	16648291	context	Tolerances Tolerances
25863	15	16648292	context	The allowed B2B deviation for all output-signals to the expected reactions is defined by the following tolerances: The allowed B2B deviation for all output-signals to the expected reactions is defined by the following tolerances:
25864	16	16648293	context	Bool: No deviation allowed Bool: No deviation allowed
25865	17	16648294	context	UInt, Int: No deviation allowed UInt, Int: No deviation allowed
25866	18	16648295	context	Float: 0.1% related to the permissible value range of the signal Float: 0.1% related to the permissible value range of the signal
25867	19	16648296	context	It must be ensured that an output reaction occurs due to an event at the input within the same calculation step. It must be ensured that an output reaction occurs due to an event at the input within the same calculation step.
25868	20	16648297	context	Conditions Conditions
25869	21	16648298	context	NVM simulation NVM simulation
25870	22	16648299	context	NVM signals NVM (non-volatile memory) output signals are used to store information being calculated in the last time sample before ECU shutdown durin NVM signals NVM (non-volatile memory) output signals are used to store information being calculated in the last time sample before ECU shutdown during ECU sleep. By reading the corresponding NVM input signals, the stored values are available in the first time sample after ECU startup again. While the ECU is awake, the value of an NVM input signal is equal to the value of the corresponding NVM output signal of the previous time sample. To simulate this signal behavior NVM input signals have to be stimulated as described below: In the first time step the value of each NVM input signal has to be stimulated with the default value defined below. Once the value of the corresponding NVM output signal is available (starting from second time step), each NVM input signal has to be stimulated with the corresponding NVM output signal (feedback loop with a delay of one time step). NVM_Input[t] = NVM_Output[t-1]
25871	23	16648300	context
25872	24	16648301	context	Input Conditions Input Conditions
25873	25	16648302	context	If not requested differently, the following default signal values must be applied during each test case. If not requested differently, the following default signal values must be applied during each test case.
25874	26	16648303	context	Signal and parameters state are added since they are not visible in SPE. As soon as the state will be added in SPE, they will not be valid anymore in Signal and parameters state are added since they are not visible in SPE. As soon as the state will be added in SPE, they will not be valid anymore in this SWRS (SPE = master).
25875	27	16648304	context	VMM1 VMMP_s_DWDRead_VVehLimBwd VMM1 VMMP_s_DWDRead_VVehLimBwd
25876	28	16648305	context	VMM2 VMMP_s_DWDRead_VVehLimFwd VMM2 VMMP_s_DWDRead_VVehLimFwd
25877	29	16648306	context	VMM3 VMMP_s_DWDRead_VVehLimReq 0 = Init 1 = No Request 2 = Write Request VMM3 VMMP_s_DWDRead_VVehLimReq 0 = Init 1 = No Request 2 = Write Request
25878	30	16648307	context	VMM4 VMMP_s_DWDRead_NumVehLimChk VMM4 VMMP_s_DWDRead_NumVehLimChk
25879	31	16648308	context	VMM6 VMMP_s_DWDRead_VVehLimProd VMM6 VMMP_s_DWDRead_VVehLimProd
25880	32	16648309	context	VMM7 VMMP_s_DWDRead_VVehLimProdReq 0 = Init 1 = No Request 2 = Write Request VMM7 VMMP_s_DWDRead_VVehLimProdReq 0 = Init 1 = No Request 2 = Write Request
25881	33	16648310	context	VMM8 VMMP_s_NVMBlck03_IniErrSt 0 = OK 1 = NOK VMM8 VMMP_s_NVMBlck03_IniErrSt 0 = OK 1 = NOK
25882	34	16648311	context	VMM9 VMMP_s_NVMBlck04_IniErrSt 0 = OK 1 = NOK VMM9 VMMP_s_NVMBlck04_IniErrSt 0 = OK 1 = NOK
25883	35	16648312	context	SRV1 VSOEM_s_VLgtStdDev SRV1 VSOEM_s_VLgtStdDev
25884	36	16648313	context	SRV2 VSOEM_s_VLgtVehNrm SRV2 VSOEM_s_VLgtVehNrm
25885	37	16648314	context	SRV3 VSOVD_s_StDrvDir DrvDirBwd = 2 SRV3 VSOVD_s_StDrvDir DrvDirBwd = 2
25886	38	16648315	context	SRV4 VSOVD_s_StTrptProt SRV4 VSOVD_s_StTrptProt
25887	39	16648316	context	SRV9 VSOVD_s_StCrExchProt SRV9 VSOVD_s_StCrExchProt
25888	40	16648317	context	SRV10 VSOVD_s_StProdMd SRV10 VSOVD_s_StProdMd
25889	41	16648318	context	SRV12 VSOVD_s_VehPwrLvl SRV12 VSOVD_s_VehPwrLvl
25890	42	16648319	context	SRV13 VSOVD_s_StPwrMd SRV13 VSOVD_s_StPwrMd
25891	43	16648320	context	NVM1 VMMP_s_NVM08Read_VVehLimFwd NVM1 VMMP_s_NVM08Read_VVehLimFwd
25892	44	16648321	context	NVM2 VMMP_s_NVM09Read_VVehLimBwd NVM2 VMMP_s_NVM09Read_VVehLimBwd
25893	45	16648322	context	NVM3 VMMP_s_NVM10Read_NumVehLimChk NVM3 VMMP_s_NVM10Read_NumVehLimChk
25894	46	16648323	context	NVM5 VMMP_s_NVM11Read_FlgVehLimVld NVM5 VMMP_s_NVM11Read_FlgVehLimVld
25895	47	16648324	context	NVM6 VMMP_s_NVM12Read_VVehLimProd NVM6 VMMP_s_NVM12Read_VVehLimProd
25896	48	16648325	context	Parameters Parameters
25897	49	16648326	context	P1 VMMP_VVL_p_VVehLimWithStdDev 0 = correction with standard deviation NOT active 1 = correction with standard deviation active 2 = correction w P1 VMMP_VVL_p_VVehLimWithStdDev 0 = correction with standard deviation NOT active 1 = correction with standard deviation active 2 = correction with 3sigma active
25898	50	16648327	context	P2 VMMP_VVL_p_VVehLimTrptProtFwd P2 VMMP_VVL_p_VVehLimTrptProtFwd
25899	51	16648328	context	P3 VMMP_VVL_p_VVehLimTrptProtBwd P3 VMMP_VVL_p_VVehLimTrptProtBwd
25900	52	16648329	context	P4 VMMP_VVL_p_VVehLimTrptProtAcv P4 VMMP_VVL_p_VVehLimTrptProtAcv
25901	53	16648330	context	P5 VMMP_VVL_p_VVehLimAdjChnAcv P5 VMMP_VVL_p_VVehLimAdjChnAcv
25902	54	16648331	context	P6 VMMP_VVL_p_VVehLimFwdDft P6 VMMP_VVL_p_VVehLimFwdDft
25903	55	16648332	context	P7 VMMP_VVL_p_VVehLimBwdDft P7 VMMP_VVL_p_VVehLimBwdDft
25904	56	16648333	context	P9 VMMP_VVL_p_VVehLimStAcvFwd P9 VMMP_VVL_p_VVehLimStAcvFwd
25905	57	16648334	context	P10 VMMP_VVL_p_SimVVehLimFwd P10 VMMP_VVL_p_SimVVehLimFwd
25906	58	16648335	context	P11 VMMP_VVL_p_SimVVehLimBwd P11 VMMP_VVL_p_SimVVehLimBwd
25907	59	16648336	context	P12 VMMP_VVL_p_SimSwt P12 VMMP_VVL_p_SimSwt
25908	60	16648337	context	P13 VMMP_VVL_p_SimSwtVVehLim P13 VMMP_VVL_p_SimSwtVVehLim
25909	61	16648338	context	P14 VMMP_VVL_p_SimVVehLimSt P14 VMMP_VVL_p_SimVVehLimSt
25910	62	16648339	context	P15 VMMP_VVL_p_SimSwtVVehLimSt P15 VMMP_VVL_p_SimSwtVVehLimSt
25911	63	16648340	context	P16 VMMP_VVL_p_SimNumVehLimChk P16 VMMP_VVL_p_SimNumVehLimChk
25912	64	16648341	context	P20 VMMP_VVL_p_SwtUseStDrvDir P20 VMMP_VVL_p_SwtUseStDrvDir
25913	65	16648342	context	P22 VMMP_VVL_p_DTCAdjChnVVehLimProdAcv P22 VMMP_VVL_p_DTCAdjChnVVehLimProdAcv
25914	66	16648343	context	P23 VMMP_VVL_p_DTCAdjChnVVehLimQTSAcvAcv P23 VMMP_VVL_p_DTCAdjChnVVehLimQTSAcvAcv
25915	67	16648344	context	P24 VMMP_VVL_p_DTCAdjChnVVehLimCRCNotVldAcv P24 VMMP_VVL_p_DTCAdjChnVVehLimCRCNotVldAcv
25916	68	16648345	context	P25 VMMP_VVL_p_SwtVVehLimCl15Avl P25 VMMP_VVL_p_SwtVVehLimCl15Avl
25917	69	16648346	context	P26 VMMP_VVL_p_VVehLimVThAvl P26 VMMP_VVL_p_VVehLimVThAvl
25918	70	16648347	context	P27 VMMP_VVL_p_SwtVVehLimVThAvl P27 VMMP_VVL_p_SwtVVehLimVThAvl
25919	71	16648348	context	P28 VMMP_VVL_p_VVehLimBwdMaxVal P28 VMMP_VVL_p_VVehLimBwdMaxVal
25920	72	16648349	context	P29 VMMP_VVL_p_VVehLimProdVThAvl P29 VMMP_VVL_p_VVehLimProdVThAvl
25921	73	16648350	context	P30 VMMP_VVL_p_AdjChnErrCodNoErr P30 VMMP_VVL_p_AdjChnErrCodNoErr
25922	74	16648351	context	P31 VMMP_VVL_p_AdjChnErrCodOutOfRng P31 VMMP_VVL_p_AdjChnErrCodOutOfRng
25923	75	16648352	context	P32 VMMP_VVL_p_AdjChnErrCodCl15Off P32 VMMP_VVL_p_AdjChnErrCodCl15Off
25924	76	16648353	context	P33 VMMP_VVL_p_AdjChnErrCodVToHi P33 VMMP_VVL_p_AdjChnErrCodVToHi
25925	77	16648354	context	P34 VMMP_VVL_p_AdjChnErrCodProdMdNotAcv P34 VMMP_VVL_p_AdjChnErrCodProdMdNotAcv
25926	78	16648355	context	P35 VMMP_VVL_p_AdjChnErrCodDrvReqAcv P35 VMMP_VVL_p_AdjChnErrCodDrvReqAcv
25927	79	16648356	context	P36 VMMP_VVL_p_AdjChnErrCodPTPwrNotOff P36 VMMP_VVL_p_AdjChnErrCodPTPwrNotOff
25928	80	16648357	context	P37 VMMP_VVL_p_VVehLimProdVNotVldValMin P37 VMMP_VVL_p_VVehLimProdVNotVldValMin
25929	81	16648358	context	P38 VMMP_VVL_p_VVehLimProdVNotVldValMax P38 VMMP_VVL_p_VVehLimProdVNotVldValMax
25930	82	16648359	context	P39 VMMP_VVL_p_SimVVehLimProdFwd P39 VMMP_VVL_p_SimVVehLimProdFwd
25931	83	16648360	context	P40 VMMP_VVL_p_SimSwtVVehLimProd P40 VMMP_VVL_p_SimSwtVVehLimProd
25932	84	16648361	context	P41 VMMP_VVL_p_SimSwtVVehLimProdSt P41 VMMP_VVL_p_SimSwtVVehLimProdSt
25933	85	16648362	context	P42 VMMP_VVL_p_SimVVehLimProdSt P42 VMMP_VVL_p_SimVVehLimProdSt
25934	86	16648363	context	P43 VMMP_VVL_p_VVehLimProdNotAcvRst P43 VMMP_VVL_p_VVehLimProdNotAcvRst
25935	87	16648364	context	P44 VMMP_VVL_p_VVehBwdTh P44 VMMP_VVL_p_VVehBwdTh
25936	88	16648365	context	P45 VMMP_VVL_p_VVehLimFwdMaxVal P45 VMMP_VVL_p_VVehLimFwdMaxVal
25937	89	16648366	context	P46 VMMP_VVL_p_AdjChnProdPreCndAcv P46 VMMP_VVL_p_AdjChnProdPreCndAcv
25938	90	16648367	context	P47 VMMP_VVL_p_VVehLimAdjChnProdAcv P47 VMMP_VVL_p_VVehLimAdjChnProdAcv
25939	91	16648368	context	P48 VMMP_VVL_p_SetDftGetErrStAcv P48 VMMP_VVL_p_SetDftGetErrStAcv
25940	92	16648369	context	P49 VMMP_VSOVD_c_StPwrMdPwrOffMd P49 VMMP_VSOVD_c_StPwrMdPwrOffMd
25941	93	16648370	context	P50 VMMP_VVL_p_WLVMaxAcv P50 VMMP_VVL_p_WLVMaxAcv
25942	94	16648371	context	P51 VMMP_VVL_p_VVehLimSigStdDev P51 VMMP_VVL_p_VVehLimSigStdDev
25943	95	16648372	context	P52 VMMP_VVL_p_DTCAdjChnVVehLimNotAcvAcv P52 VMMP_VVL_p_DTCAdjChnVVehLimNotAcvAcv
25944	96	16648373	context	Predefinitions Predefinitions
25945	97	16648374	context	VVLPC1 Driving direction backward IF OR(1,2) 1) the driving direction is backwards 2) the driving direction is smaller zero THEN the driving VVLPC1 Driving direction backward IF OR(1,2) 1) the driving direction is backwards 2) the driving direction is smaller zero THEN the driving direction is backwards VVLPC1
25946	98	16648375	context	VVLPC2 CANCRC check is successful To verify the value of adjustment channel VVehLimFwd and VVehLimBwd with CRC checksum a CANCRC check is implem VVLPC2 CANCRC check is successful To verify the value of adjustment channel VVehLimFwd and VVehLimBwd with CRC checksum a CANCRC check is implemented. IF value fwd and value bwd are leading to a checksum THEN the CANCRC check is successful VVLPC2
25947	99	16648376	context	CANCRC check: - the CRC uses the start value 65535 - the CRC uses the polynom 50585 (=CANCRC) - the CRC starts with the value for fwd und continues CANCRC check: - the CRC uses the start value 65535 - the CRC uses the polynom 50585 (=CANCRC) - the CRC starts with the value for fwd und continues with the value for bwd algorithm: 1) extract byte3 and shift it 16 positions to the right 2) XOR-connect the result with the start value 3) repeat this step for (in total) 8 times: bitshift 1 position to the left and extract bit 16. if bit 16 is - 0, then AND-connet the result with 0xFFFF (clear the upper 16 bits) - 1, then XOR-connect the result with the polynom and AND-connect it with 0xFFFF (clear the uper 16 bits) 4) continue with byte2, repeat step 1-3 for byte 2 and use the result of byte 3 as start value 5) continue with byte1, repeat step 1-3 for byte 2 and use the result of byte 2 as start value 6) continue with byte0, repeat step 1-3 for byte 2 and use the result of byte 1 as start value 7) continue with byte3 of value for bwd, use the result of byte0 of fwd as start value. ... at the end, convert the result to a uint16.
25948	100	16648377	context	Reactions Reactions
25949	101	16648378	context	VVL1 VVL_s_LgtLimV_StAcvFwd 0 = Passive 1 = Active 3 = Failure 6 = Init VVL1 VVL_s_LgtLimV_StAcvFwd 0 = Passive 1 = Active 3 = Failure 6 = Init

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